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Xilinx and Infineon are collaborating to offer power solutions for Zynq® UltraScale™+ MPSoC and RFSoC families

Electronics Maker by Electronics Maker
February 27, 2019
in Electronics News
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Munich, Germany – 26 February 2019 – Xilinx Inc. and Infineon Technologies AG (FSE: IFX / OTCQX: IFNNY) have collaborated to provide scalable power for the Xilinx ® Zynq ® UltraScale™+ MPSoC and RFSoC families. Infineon is contributing its leading power management integrated circuit (PMIC) IRPS5401 to the Xilinx ZCU104 and ZCU111 Evaluation Kits. The ZCU104 evaluation kit with Zynq UltraScale+ MPSoC helps jumpstart designs for embedded vision applications such as surveillance, advanced driver assisted systems (ADAS), machine vision, augmented reality (AR), drones and medical imaging. The ZCU111 evaluation kit features the Zynq UltraScale+ RFSoC for rapid RF-Type analog design prototyping for wireless, cable access, early-warning radar and other high-performance RF applications.

These two evaluation kits allow a quick time to market for system developers, providing power delivery, power sequencing, fault management and telemetry. Xilinx’s evaluation kits integrate 15 to 30 components for complete power delivery from eight to 30 power rails for small form factor applications.

The Xilinx Zynq UltraScale+ RFSoC features an analog-to-digital signal chain supported by a DSP subsystem for flexible configuration by the analog designer. This leads to a 50 to 75 percent reduction in system power and system footprint, along with the needed flexibility to adapt to evolving specifications and network topologies. The Xilinx Zynq UltraScale+ MPSoC is equipped with a quad-core ARM application processor, a dual-core real-time processor and a Mali graphics processing unit, making it the most advanced SoC in the market.

The evaluation kits are equipped with Infineon’s IRPS5401 for power to advance FPGA/SoCs needing multiple voltage supplies for 10 W to 50 W of total power. The DC/DC PMIC with multiple outputs is used together with a uDrMos integrated OptiMOS5 power stage to allow scalability in order to meet the V core voltage needs and other input voltages of FPGA/SoC families. The integration includes multiple DC/DC regulators with FET and drivers, DDR3/DDR4 LDOs, full fault management for both the input and output, voltage, current and power telemetry. Additional features include integrated power sequencing delay for both power up and power down and integrated digital compensation to minimize external component count.

Tags: PSoC and RFSoC families
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