Toshiba achieves 16 percent place and route area reduction and 25 percent lower power consumption with shorter place and route turnaround time
SAN JOSE, Calif., April 25, 2016
Cadence Design Systems, Inc. today announced that Toshiba Corporation has adopted the Cadence® Innovus™ Implementation System for its memory controller’s production design project. The tool enabled Toshiba to achieve an optimal target performance while creating a 16 percent smaller place and route (P&R) area for random logic with 25 percent lower power consumption when compared with its previous solution.
The Innovus Implementation System handles challenging, highly complex designs and addressed Toshiba’s requirements utilizing technologies such as the GigaPlace™ solver-based placement technology, GigaOpt™ low-power optimization and CCOpt™ concurrent clock and datapath optimization engines. The Innovus Implementation System is built on a massively parallel architecture, allowing core algorithms to utilize multi-threading and distributed computing to provide Toshiba with a significant capacity improvement and speedup on industry-standard hardware. These advanced capabilities enabled Toshiba to effectively implement its own custom libraries to meet aggressive power and area targets while also reducing P&R turnaround time.
“Reduction of chip size and power consumption is quite crucial for memory controller designs, especially when targeted for mobile applications. Through our intensive collaboration with Cadence, the Innovus Implementation System has proven to be an effective option for our mobile memory controller design,” said Kazunari Horikawa, senior manager of the Design Technology Development Department, Mixed Signal IC Division, Storage & Electronic Devices Solutions Company at Toshiba Corporation. “We plan to apply the Innovus Implementation System to other product designs as well, based on the positive results we’ve experienced with our current design.”
“The Innovus Implementation System speeds Toshiba’s implementations by providing a best-in-class place and route system with massively parallel and multi-threaded optimization engines,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “Hitting aggressive power and area targets while reducing turnaround time is critical so that Toshiba can deliver its complex memory controller designs to market within tight deadlines.”
