Native System Verilog-based VIP for Sound Wire Expands Portfolio of VIP for Mobile Applications and Offers Built-in Coverage, Verification Plan and Protocol-aware Debug
New Delhi, March 13, 2015– Synopsys, Inc. (NASDAQ: SNPS) announces the availability of verification IP (VIP) for the MIPI® Alliance SoundWireSM1.0 specification. Synopsys VIP for MIPI Sound Wireis based on a native System Verilog UVM architecture to enable IP, subsystem and system-on-chip (SoC) designers to easily integrate their designs and accelerate verification performance. Synopsys VIP for MIPI Sound Wire also includes System Verilog source code test suites to eliminate the tasks of developing a verification environment and the required tests. Complete with verification plans, built-in coverage and support for protocol-aware debug, Synopsys VIP for MIPI Sound Wire accelerates verification closure for designers of low power audio and control interfaces used in mobile and mobile-influenced devices.
“MIPI Sound Wire consolidates many of the key attributes available in mobile and PC industry audio interfaces and introduces a scalable, low power, two-pin multi-drop architecture that can be used to transport multiple audio streams along with embedded controls and commands,” said Joel Huloux, chairman of the board of MIPI Alliance. “The release of Synopsys VIP for MIPI Sound Wire strengthens the ecosystem, required to facilitate early adoption and fast development of MIPI Sound Wire-based designs.”
“Asan active contributing member of the MIPI Alliance, we have collaborated closely with all working groups to develop VIP that allows leading-edge SoC design teams to address the increasingly demanding process of protocol compliance verification; this accelerates verification closure and time to market for mobile and mobile-influenced devices, ”said Debashis Chowdhury, vice president of R&D for the Synopsys Verification Group. “The release of the Synopsys VIP for MIPI Sound Wire underscores our continued investment in our VIP portfolio to enable increased design quality and faster, more complete verification closure.”
