Models Available Immediately to Semiconductor and EDA Industries Through a Synopsys Open-source License
BANGALORE, India – September, 7, 2016 — Synopsys, Inc. (Nasdaq: SNPS) today announced extensions to its open-source licensed Interconnect Technology Format (ITF), which enables additional modeling of complex parasitic effects between device structures and interconnect layers at the advanced 10-nanometer (nm) and 7-nm process nodes. These new models will enable parasitic extraction tools to accurately capture silicon variation that impacts timing and reliability analysis. Synopsys collaborated with members of the Interconnect Modeling Technical Advisory Board (IMTAB) [member list available at www.imtab.org], an IEEE-ISTO Federation Member Program, to refine and ratify these new extensions. They are available in the Synopsys ITF version 2016 through an open-source license.
“Dealing with increasing variation and complexity at 10-nm and below process nodes requires continuous modeling innovation as well as providing usable standards to facilitate easier adoption,” said Bari Biswas, vice president of Engineering for extraction solutions at Synopsys and chair of IMTAB. “Working together with IMTAB members and leading foundries, Synopsys has taken another big step forward by enriching the ITF format with refreshed and extended models to support effects of advanced multi-color patterning and 3D FinFET devices, while ensuring the simplicity to enable efficient enablement and deployment.”
The new IMTAB-ratified extensions to ITF include:
- Gate-to-diffusion device parasitic modeling enhancements for required accuracy at 10-nm/7-nm
- Color-aware thickness variation extension for triple and quad color patterning
- Density-aware thickness variation improvement for enhanced modeling of CMP effects
- Silicon coverage-based via resistance for improved accuracy based on silicon dimensions
- Dielectric fill modeling for accurate coupling capacitance extraction of ultra-low dielectrics
“ITF has been embraced by a growing number of leading semiconductor and EDA companies since its inception in 2010 as an interoperable industry standard for parasitic modeling to reduce cost of tool development and speed design cycles,” said Marco Migliaro, president, IEEE-ISTO. “The IMTAB consortium’s ratification of the latest ITF extensions underscores its commitment to extending these interoperability benefits to advanced 10-nm and 7-nm nodes. IEEE-ISTO looks forward to supporting IMTAB in its mission and commitment to expand the benefits of the ITF common open-source licensed modeling format within the industry.”
