Enablement Includes Industry-Leading IC Compiler II P&R Solution and DesignWare Embedded Memory IP
Bangalore., June 21, 2017 —
Synopsys Design Platform supports advances in GLOBALFOUNDRIES’ 7-nm low-power technology and Self-Aligned Double Patterning (SADP)
IC Compiler II enhancements include router advancements tuned to realize power-performance benefits of the 7-nm process
Familiar flow steps enhanced to meet new 7-nm requirements and implemented on design example including high performance memories
High-speed, high-density, ultra-density DesignWare Memory Compilers and HPC Design Kits deliver superior performance, power and area
Synopsys, Inc. (Nasdaq: SNPS) today announced the enablement of the Synopsys Design Platform and DesignWare® Embedded Memory IP on GLOBALFOUNDRIES 7-nm Leading-Performance (7LP) FinFET process technology. Synopsys and GF collaboration on the new process addressed several new challenges specific to the 7LP process. This process is expected to deliver 40 percent more processing power and twice the area scaling compared to GF’s 14nm FinFET process. Designers of premium mobile processors, cloud servers and networking infrastructure can take advantage of these benefits by confidently deploying the silicon-proven Synopsys Design Platform and Embedded Memory IP.
“GF’s leading-performance 7-nm platform is exceeding initial performance targets and is now ready for customer designs,” said Alain Mutricy, senior vice president of product management at GF. “GF and Synopsys have collaborated to provide designers with tools and methodology that fully leverage the power and highest absolute performance of our 7LP technology, and will allow customers to create innovative products across a range of high-performance applications.”
GF and Synopsys worked together to ensure support of the comprehensive suite of Synopsys Design Platform digital implementation solutions for GF 7LP, including Design Compiler® Graphical synthesis, IC Compiler™ II place-and-route, IC Validator physical verification, PrimeTime® static timing analysis and StarRC™ extraction. To enable designers to achieve the full benefit of the GF 7LP process, the Synopsys tools employ advanced techniques including color track generation, pin color alignment checking and legalization, mixing of single-height and double-height physical boundary cells, power grid alignment to track and color-track aware routing.
The two companies are also collaborating on the development of Synopsys DesignWare Memory Compilers to deliver leading performance, power, area and yield for GF’s 7-nm process technology. This joint effort consists of optimizing the GF 7LP process design rules and line patterns to achieve the best results. Early versions of the memory compilers will be on the GF 7LP process qualification vehicle.
“Synopsys and GF have always worked closely to address our customers’ needs, including collaborations on FDSOI and 14-nm FinFET processes,” said Michael Jackson, corporate vice president of marketing and business development in the Design Group at Synopsys. “With today’s announcement, we are ready to enable designs on the 7LP process. We will continue to collaborate and ensure that our customers can get superior quality of results and faster time to results by using the Synopsys Design Platform and DesignWare Embedded Memory IP.”