By Kazim Peker and Altug Oz, Analog Devices, Inc
The requirements of higher system bandwidth and resolution in a variety of applications from communications infrastructure to instrumentation drive up the demand for connecting multiple data converters in an array form. Designers must find low noise and high accuracy solutions to clock and synchronize a large array of data converters using the common JESD204B serial data converter interface.
Clock generation devices containing jitter attenuation functions, internal VCOs, and a multitude of outputs and many synchronization management functions, are now coming to market to address this system problem. In many real-life applications, however, the sheer number of required clocks in a data converter array exceeds what may be feasible to obtain from a single IC component. Designers often resort to connecting multiple clock generation and clock distribution components together, thus, creating a broad “clock tree”.
This article provides a real-life case study of how to build a flexible and re-programmable clock expansion network, that maintains not only an excellent phase noise/jitter performance, but also passes-on the required synchronization information from the 1st device of the clock tree to the last one with deterministic control.
Introduction
The evolution of wireless communications systems from 3G to 4G and LTE (and 5G, currently under specification discussions) have been critical technology drivers for high speed data conversion and synchronization. There is a confluence of factors that push up the required data bandwidths in cellular base stations. The primary factors are the growth in the number of subscribers, demand for richer multimedia content, and new applications in machine-to-machine communications using the global cellular infrastructure. As a consequence, designers are looking at new and innovative RF transceiver architectures with higher channel counts using techniques such as active antenna designs, massive MIMO and advanced beam forming.
Systems with large numbers of inputs and outputs make use of multiple transmission paths and require large counts of ADC and DAC components. Given the scale of data conversion requirements, sample clock generation and synchronization becomes a significant design challenge. In complex systems, the number of clock signals required can easily increase from just a few to hundreds, as can be seen in Figure.1.
JESD204B standard defines a serial data interface, which is used to reduce the number of data inputs/outputs between wideband data converters and other system ICs. This reduction of data I/O quantity addresses the problem of interconnecting high speed, high bit count data converters. The ability of offer wideband data converter with fewer interconnects simplifies the PCB layout and allows smaller form factor realization without impacting overall system performance. These improvements are important to address the system size and cost constraints of most of the applications, including wireless infrastructure, portable instrumentation, military applications, and medical ultrasound equipment.
System Level Considerations
In complex systems with large data converter arrays, the increasing volume of data to be processed requires high SNR (Signal-to-Noise-Ratio) links from antenna to processing units. From a clocking perspective, the SNR is limited by the phase noise of the sampling clock. Poor phase noise performance may degrade the system performance by creating jitter and increasing EVM (Error Vector Magnitude), and thus, severely decreasing SNR. In general, clock signal quality is specified in jitter, which is defined as the integration of phase noise over a set bandwidth of interest.
Typically, phase noise integration limits are 10’s of kHz to 10’s of MHz, however broadband noise is also critical, because high clock signal noise floors will also affect the SNR of the system. A poor sampling clock may also have spurious signal content, which will degrade the SFDR (Spurious Free Dynamic Range). And finally, sampling clock quality should not only be defined in the frequency domain, but also in time domain, considering parameters such as duty cycle and rise/fall time.
These are the basic system requirements for a sampling clock. However in large data converter arrays and when synchronization is required between the clocks for different arrays, inter-channel skew becomes the critical requirement. The performance in such systems relies on synchronized data arrays and therefore, is sensitive to the skew between different data converters.
Power consumption is another consideration. Higher power consumption decreases system efficiency, leads to increased temperature and cooling costs, and, potentially, to higher failure rates. From a commercial standpoint, the part count and the board space are also important and should be controlled
