Atrenta, the leading provider of SoC Realization solutions for the semiconductor and consumer electronics industries, has expanded its R&D facility in Noida, UP. The new facility houses Atrenta’s current staff and meets near-term growth requirements, keeping pace with the company’s global expansion plan. Atrenta India is a major development hub for the company’s leading edge products – SpyGlass®, GenSys® and BugScope™ – that improve complex system on chips (SoCs) fueling today’s consumer electronics revolution.
Grand Opening of Atrenta India’s New Expanded R&D Facility
Atrenta Noida employees celebrated the relocation to its new expanded R&D facility, where the office has been operational since April this year. Dr. Ajoy Bose (Chairman, President and CEO, Atrenta) cut the inaugural ribbon at the facility along with Mr. Sushil Gupta (Vice President and Managing Director, India) and the team, in the presence of Atrenta Noida employees. The new office has been built to provide high-class working spaces and better facilities, and a supportive atmosphere for R&D and other teams.
Atrenta has broken new ground in serving the needs of the SoC Realization market
SoC Realization forms a strong connection between the worlds of System Realization, where system concepts are first defined in both hardware and software, and Silicon Realization, where designs are implemented in silicon. SoC Realization is where the architecture of the semiconductor device is defined, the semiconductor IP, or building blocks for the chip, are chosen and the design is matured to a stage where it is ready to be handed off to implementation. It forms the pipeline between new SoC concepts and silicon.
Atrenta focuses on the SoC Realization part of the flow to facilitate the anticipated growth in the electronics industry in the years ahead. This area forms the connection between the heretofore isolated tasks of System Realization and Silicon Realization. Without this connection, true top-down design is not possible. Without the efficiencies of such an integrated design flow, the cost of SoC design will increase exponentially, resulting in a dramatic slow-down in the growth of the electronics sector.
Rising complexity of SoC design and IP reuse
SoC design promises to revolutionize a vast array of products and markets, but the cost of design for SoC devices is growing at a rapid pace. Shrinking market windows necessitate reuse of semiconductor IP, either from third-party sources or prior internal designs. But the quality and completeness of this IP is often not completely known. Structured design methodologies that focus on early identification and correction of design issues, rigorous methods to qualify semiconductor IP, and automated approaches to assembling the components of an SoC promise to address many of the cost and schedule challenges. Atrenta is in exactly the right place to address the ever-increasing complexity of SoC design.
SpyGlass from Atrenta
SpyGlass is Atrenta’s platform for RTL signoff. It is used by virtually all SoC design teams to ensure that the power, performance and cost of their SoC is as good as it can be prior to handoff to detailed implementation. SpyGlass is also used to select and qualify semiconductor IP – a major challenge for all SoC design teams.
The SpyGlass product family has become the de facto standard to ensure a design is implementation ready. Its use as a reference standard for semiconductor IP quality is also well documented and growing. The GenSys product family is establishing a complete methodology for automated chip assembly and RTL restructuring – critical ingredients for SoC Realization. And the new BugScope product completes the picture by addressing functional verification at RTL. Atrenta is poised to be the first broad-line supplier in the emerging SoC Realization market.
