An upcoming Samsung device codenamed SM-G900S will have 2K or 2560x1440p resolution. This is the highest resolution for any smartphone, as the current maximum is 1920x1080p.
It is said that Samsung’s upcoming Galaxy S5 smartphone will have a 5.2-inch display. This will mean pixel density of 560ppi, the highest in any smartphone available in the market. Currently, HTC One boasts of highest pixel density among smartphones – 469ppi.
However, Galaxy S5 will not be the first 2K phone in the market. Chinese manufacturer Vivo is slated to launch the world’s first smartphone with 2K resolution. The successor of HTC is also rumoured to have 2K resolution screen and hit the market in February next year.
The benchmark test also shows that the upcoming Samsung model will run on a 2.46GHz quad-core Snapdragon 800 chipset and come with Adreno 330 graphics processor. Earlier reports have said that Samsung will debut its 64-bit processor with the Galaxy S5. This has given rise to speculation that the smartphone will come in two variants – one with Snapdragon 800 processor and the other with a 64-bit chip.
According to another report (by Japanese technology website EMSOne), Samsung has asked three companies – Taiwan’s ODM Catcher Technology and Ju Teng as well as China’s BYD – to manufacture 10-30 million metal unibody shells for Galaxy S5. Recently, images of a metal frame for an upcoming Samsung device also leaked on the internet.
According to previous rumours, Galaxy S5 will have a 16MP camera and may have a water-resistant body.
Vishay Intertechnology’s -20 V P-Channel Gen III MOSFET is First in 2.4 mm by 2.0 mm by 0.4 mm MICRO FOOT® Package Size
For Mobile Computing Devices, Space-Saving MOSFET Offers Low On-Resistance Down to 8.0 mΩ at 4.5 V
Vishay Intertechnology, Inc. (NYSE: VSH) today extended its offering of TrenchFET® p-channel Gen III power MOSFETs with the industry’s first -20 V device in the 2.4 mm by 2.0 mm by 0.4 mm CSP MICRO FOOT® package size. Designed to increase efficiency and save space in mobile computing devices, the Vishay Siliconix Si8851EDB offers extremely low on-resistance of 8.0 mΩ and 11.0 mΩ at -4.5 V and -2.5 V gate drives, respectively.
The Si8851EDB‘s p-channel Gen III technology, in combination with MICRO FOOT’s packageless CSP technology and 30-pin design and layout, provides the lowest on-resistance possible for a given outline area. Compared to the closest competing 2 mm by 2 mm by 0.8 mm device, the Si8851EDB combines a 50 % thinner profile with almost half the on-resistance at a 4.5 V gate drive, providing 37 % lower on-resistance per package size. Offering similar on-resistance to 3.3 mm by 3.3 mm by 0.8 mm MOSFETs, the Si8851EDB provides a 56 % smaller outline and at least a 30 % lower on-resistance per package size.
With its slim 0.4 mm profile, the device released today is optimized for load and battery switches in power management applications for tablets, smartphones, and notebooks. The Si8851EDB‘s low on-resistance allows designers to achieve lower voltage drops in their circuits — promoting more efficient use of power and longer battery run times — while its compact footprint saves valuable PCB space. High typical ESD protection to 6 kV helps protect handheld devices against static charges, while ensuring safe part handling during the manufacturing process. The MOSFET is halogen-free according to the JEDEC JS709A definition and compliant to RoHS Directive 2011/65/EU.
