Open source design of computer chipsets RISC-V is becoming a global movement with India as a leading player. Following the demand, Ventana Micro Systems, the RISC-V Performance Leader, is enabling customer innovation in the realm of high-performance computing and develops some of the world’s highest performance CPUs, and providing the option to take them in chiplet form for rapid productisation. Ventana has created an innovative RISC-V architecture that addresses the market need for a high-performance, customizable and secure processor.
In this exclusive interview, Travis Lanier, Vice President, Ventana Micro spoke to Electronics Maker about RISC-V development in India and how Ventana is driving innovation in this segment.
Can you provide details on Ventana’s business presence and activities in India?
Ventana has a significant and growing presence in India, particularly within tech hubs Whitefield (Bengaluru) and Kothrud (Pune). Our engineering, sales, and business teams in India are expanding quickly to address the increasing demand for RISC-V solutions. We are also becoming a thought leader here. For instance, a few weeks ago we gave a keynote talk at the high-profile conference SemiconIndia, inaugurated by Honorable Prime Minister, Shri Narendra Modi.
What is the current situation of the Indian semiconductor market with respect to RISC-V?
RISC-V has huge momentum worldwide, especially in India, China, Europe, and the US. Many companies have recognized that CPU ISA is a fundamental piece of technology that should not be controlled by one or two commercial entities. The benefit of being an open standard is that it can evolve much faster than commercial ISAs. The flexibility and cost benefits are clear, which is why startups to tier one semiconductor companies are now designing with RISC-V.
How is RISC-V better than ARM in the present Indian chip industry?
RISC-V is gaining traction over ARM in the Indian chip industry thanks to its open-standard architecture. Unlike the ARM architecture controlled by a few entities, RISC-V allows for greater innovation freedom with its open ISA developed within a global community. This open structure offers strategic independence from foreign proprietary technologies and eliminates expensive licensing fees.
One specific example would be accessibility to research at universities. Legacy architectures owned by a company would typically engage with a select couple of universities, and nobody else would be able to do deep research due to both access and legal issues. RISC-V ignited a storm of research into CPU microarchitecture, and you can see India leading the way here.
How is RISC-V fueling the development of startups in India?
RISC-V provides startups in India with increased strategic independence, freedom to innovate, and cost savings. The flexibility it offers can lead to breakthrough innovations and boost domestic manufacturing, both crucial for startups looking to differentiate themselves. The ecosystem built around RISC-V also aids in fostering innovation. Specifically, you can now get started on new designs without the large cost of entry, or having the final commercial license hanging over your head if you get going with one of their “getting started” licenses.
How is Ventana driving innovation in the sector in its research and development in India, and what are the product offerings?
Ventana is leading the way in transitioning data centers and others to RISC-V. We hold strategic roles in developing the ISA standard within RISC-V International and have contributed extensively to software initiatives, such as RISE and various open source projects. Much of this work is being done by our team in India.
Ventana has also been a pioneer in chiplet integration standards, making chip development simpler and faster for various applications such as Data Centers, Automotive, 5G, AI, and Client applications. Our Veyron solution is the world’s first data center class RISC-V CPU product family, offering unmatched performance. We offer Veyron both as IP that can be integrated in your own SoC, or a compute chiplet product that can be used to quickly and efficiently packaged with complementary chiplets to create custom computing solutions.
What are the key trends driving RISC-V momentum and how will you evaluate its future?
The key trends pushing RISC-V momentum are the global shift toward open-standard architectures, the need for strategic independence from proprietary technologies, cost-saving potentials, and the desire for rapid innovation. Tools and IP are maturing and engineers are becoming comfortable with RISC-V, which is leading to a surge in adoption, challenging established ISAs like ARM.
To dig in a little further, most are familiar with the commercial incentives to adopt an open standard ISA: you are not held captive to the whims of one company for the cost of your computing solution. But there are two other big drivers. Firstly, we already talked about how RISC-V is causing a renaissance in computer architecture research. RISC-V is now being taught at most universities, so you have many graduating engineers already very familiar with RISC-V. The second big driver is the need for national sovereignty, which requires the ability for you to adapt the technology to your needs. You don’t get that from a commercial ISA.
Do you have competitors in this segment? What is your unique selling point?
Certainly, there are competitors for Ventana in RISC-V. That’s what makes RISC-V compelling – you have multiple options and teams competing with each other to make the best designs. Ventana has a compelling solution – we’ve seen some out there copying our message on highest performance and chiplets. That’s flattering, because it means we are onto something. Some of our differentiation is that we have the highest performance RISC-V solution. The IP is available today, and we have a roadmap to keep that lead. We are also a pioneer in chiplets. One really compelling differentiator is the team we have: many at Ventana are the same people who created the first 64-bit Arm processor and got it deployed to the data center. Ventana brings the know-how to bring a new ISA to the finish line, and we have a significant head start over others looking to enter the RISC-V high performance segment.
Travis Lanier is the Vice President of Ventana with over 27 years of experience in CPU development. He began his career at AMD, where worked on the K5, K6, and Athlon processors. He then spent over a decade at Arm, where he worked in both engineering and product management on many key technologies, including BIG.little, NEON, and Arm’s early data center efforts with Cortex-A15 and later their first 64-bit processors. In 2011 he joined Qualcomm, where he managed their technology roadmap for a broad portfolio of processor technologies, including CPU, DSP, AI, security, and compilers across their entire portfolio of products, including mobile, automotive, and data center. Travis earned an MS in computer engineering from the University of Texas at Austin, and BS in electrical engineering from Louisiana State University.