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Renesas Demonstrates Deterministic Deep Database Search Engine Interoperating with Xilinx’s FPGA-based Packet Processor at Japan IT Week 2015

Electronics Maker by Electronics Maker
April 27, 2015
in Electronics News
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Xilinx FPGA board (left) and Renesas evaluation board (right)
Xilinx FPGA board (left) and Renesas evaluation board (right)

Renesas S-Series Search Engine Together with Xilinx’s SDNet-Generated Packet Processing Architectures Enables Complete System Solutions for IoT Network Infrastructures

SANTA CLARA, Calif., April 27, 2015 — Renesas Electronics Corporation, a premier provider of advanced semiconductor solutions, today announced it is demonstrating its Deterministic Deep Database Search Engine interoperating with Xilinx’s FPGA-based packet processor at Japan Week 2015. Developed in close collaboration with Xilinx, this solution supports up to 200 Gbps of packet processing and includes advanced classification capabilities with over one million rules for application identification and access control lists to address the explosion of traffic and data generated by the Internet of Things (IoT) sensors and devices.

“The new platform will combine the benefits of our network search engine with Xilinx’s flexible SDNet®-based packet processor and reference designs to provide customers with an easy-to-implement, customizable solution for IoT network infrastructure that allows them to accelerate their time to market,” said Ichiro Tomioka, Vice President, Chief of OA & ICT Business Division, Renesas Electronics Corporation.

The Renesas S-series network search engine (R8A20686BG) provides two high-speed Interlaken Look-Aside ports and two independent memory banks enabling multi-threaded configurations. Based on over ten years of Renesas’ extensive experience in ternary content addressable memory (TCAM) technology, the search database is fully scalable, while throughput and latency remain deterministic without the need for software realignment.

Xilinx’s SDNet development environment allows the generation of flexible programmable packet processors on an FPGA and scales performance of individual packet processing threads from 1 Gbps to 100Gbps and beyond. The Xilinx packet processor enables access to any number of fields in the packet header or payload.

“As the deployment of Network Functions Virtualization (NFV) solutions begins, the unique capability of Xilinx’s in-service programmable packet processing, combined with dynamic NSE database table management, will simplify configuration and management of network equipment for IoT traffic processing,” said Hemant Dhulla, Vice President of Wired and Data Center Communications at Xilinx.

Renesas and Xilinx will demonstrate this solution at the Embedded Systems Expo at during Japan IT Week, May 13-15, 2015.

Tags: FPGASemiconductor & IC
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