Bengaluru, India | July 23, 2025 — The 9th IEEE International Test Conference India (ITC India 2025) concluded on a high note in Bengaluru, held between 20th and 22nd July, reaffirming its role as a strategic platform to advance India’s growing presence in the global semiconductor ecosystem.
Bringing together hundreds of professionals from across industry and academia, this year’s edition spotlighted the latest breakthroughs in semiconductor test, validation, simulation, and system-level reliability. With a diverse lineup of global speakers, parallel technical tracks, panel discussions, and live technology showcases, the event served as a crucial bridge between research, application, and industry demand.
Supported by leading technology companies including Caliber Interconnects, Siemens, Tessolve, Google, Cadence, Synopsys, Qualcomm, DeFT, Soliton, Anora, Mirafra, Advantest, and Maven Silicon, the conference created a dynamic environment for learning, networking, and collaboration. Exhibitors demonstrated a wide array of products and solutions spanning AI-enabled test automation, advanced DFT methodologies, post-silicon validation tools, yield optimization, and system reliability platforms.
Organized with the technical backing of IEEE Bangalore Section, along with IESA, VLSI Society, and other strategic partners, the event saw increased participation and positive feedback, with attendees noting stronger footfall, richer content, and valuable peer engagement compared to previous editions.
One of the most impactful moments of the event was the final day keynote by Mr. Suresh Babu K, Managing Director, Caliber Interconnect Solutions, titled “From Silicon to Solutions: The Societal Impact of Semiconductor Leadership.” His address mapped out the future of the semiconductor industry by highlighting:
• The Global Semiconductor Mission and India’s rising role
• Time-to-market acceleration and quality assurance as competitive levers
• Challenges in test scalability
• The evolution of test—from design to validation
• Strategic priorities and ecosystem collaboration to fuel innovation and self-reliance
He emphasized that India’s engineering services companies must adapt continuously to technology shifts across end-product lifecycles, and pointed to the significant job opportunities emerging in this evolving test ecosystem.
“Our readiness to provide design-to-validation solutions will define India’s contribution to the global semiconductor value chain,” said Mr. Suresh Babu, urging greater collaboration among industry stakeholders, startups, and academia.
Global Thought Leaders at the Forefront of Innovation. Other notable keynotes that enriched the conference included
• “The Right Testing Strategy Can Save Designs” by Nitza Basoco, Teradyne
• “Rethinking Silicon Test to Reduce DPPM and SDC” by Dr. Sreejit Chakravarty, IEEE Fellow & Distinguished Engineer, Ampere Computing (USA)
• “Transformative Design-for-Test Technologies for Silicon Lifecycle Management” by Janusz Rajski, Siemens EDA
• “The Future of AI Hardware Enabled by Advanced Packaging” by Raja Swaminathan, AMD (USA)
• “Enabling Efficient Prototyping for Fabless Design Houses” by Rajesh V, Senior VP – Test & Product Engineering, Tessolve (India)
These sessions underscored the critical role of innovation in reducing test escape rates, improving yield predictability, and ensuring robustness in next-generation chips, especially as AI, edge computing, and automotive electronics demand more complex test coverage.
Strengthening India’s Semiconductor Future
The conference fostered cross-disciplinary conversations around:
• AI/ML in test analytics
• Secure test infrastructures for hardware IP
• EDA-cloud synergy for scalable simulation
• Prototyping efficiency for fabless startups
As India makes bold strides toward becoming a global semiconductor hub, IEEE ITC India 2025 has once again proven to be a vital ecosystem enabler — connecting visionaries, technologists, and innovators who are defining the future of silicon reliability and performance.
Saravanam J
9880974765
