SAN JOSE, Calif., January 13, 2015—Cadence Design Systems, Inc. announced that it plans to exhibit its latest Sigrity™ signal analysis and power integrity technologies at this year’s DesignCon at booth 515 fromJanuary 27 to 30, 2015, in Santa Clara, CA.
To register for the conference, visit http://www.designcon.com/santaclara/registration/
WHAT:
The following technologies are scheduled for demonstrations at the show:
- Constraint-driven power integrity design and analysis featuring decap placement guidance and DRC markers located where IR drop is out of spec
- Power-aware memory interface design and analysis of the latest DDR and LPDDR interfaces
- Multi-gigabit serial link design and analysis featuring compliance tests for PCI Express®, MIPI, and USB
- Chip/package/PCB power delivery network (PDN) co-simulation linking Cadence® Voltus™ technology with Cadence Sigrity technology
Cadence is scheduled to deliver several speaking sessions to discuss new developments in these technologies and how they can help solve today’s complex PCB and IC packaging challenges. The scheduled Cadence speaking sessions are:
ERC and SRC—Advanced PCB Layout Checks for Power-Aware Signal Integrity
Speaker: Joy Li, Solution Flow Architect
Date: Wednesday, January 28
Time: 2:50pm – 3:30pm
Location: Chiphead Theater
Panel: System-Level Modeling for IP Enablement
Speaker: Brad Brim, Senior Staff Product Engineer
Date: Wednesday, January 28
Time: 3:45pm – 5:00pm
Location: M2
Designing High-Performance Interposers with 3-Port and 6-Port S-Parameters
Speaker: Phillip Pun, Principal Design Engineer
Date: Thursday, January 29
Time: 8:30am-9:10am
Location: M2
A Fast and Accurate Approach to Power Integrity Analysis for Complex SiP
Speaker: Taranjit Kukal, Product Engineering Architect
Date: Friday, January 30
Time: 10:40am-11:20am
Location: Ballroom E/F
WHEN:
January 27 – 30, 2015
WHERE:
Booth #515 at DesignCon 2015, Santa Clara Convention Center,
5001 Great America Parkway, Santa Clara
