User conference provides a platform for design engineers to exchange ideas and best practices
Bangalore, INDIA, August 20, 2015—Cadence Design Systems (India) Pvt. Ltd., a subsidiary of Cadence Design Systems, Inc, successfully concluded its annual flagship user conference CDNLive India 2015. The conference brought together users and industry experts from semiconductor and electronics product and design services companies, and featured keynotes from Texas Instruments and Samsung. The winners of CDNLive India 2015 Best Paper Awards were also announced.
The two-day conference, held on August 18 and 19, provided an opportunity for delegates to network with peers, share best practices, understand the latest solutions and discover new techniques to address their most difficult design challenges.
Speaking about the conference, Jaswinder Ahuja, corporate vice president and managing director of Cadence India, said, “CDNLive India is one of the most important user conferences for the electronics industry today, with a strong focus on technical content. CDNLive provides an opportunity for our customers and partners to exchange ideas, network, share best practices and learn new ways to address their specific design challenges. We received strong interest in CDNLive India right from the Call for Papers process to the live events, which reflects the growth of the semiconductor and electronics design community in India.”
On Day 1, August 18, Lip-Bu Tan, president and CEO of Cadence, gave a keynote address on “Innovation in System Design Enablement.” This presentation was followed by a technology keynote by Chin-Chi Teng, corporate vice president of the Digital and Signoff Group at Cadence. The guest keynote on Day 1 was Mahesh Mehendale, MCU Chief Technologist and director of Kilby Labs India at Texas Instruments, who addressed the audience about ultra-low power challenges in the context of IoT. On Day 2, August 19, Nimish Modi, senior vice president, Marketing and Business Development at Cadence spoke about the latest in system design enablement. Mike Stellfox, a fellow in the System and Verification Group at Cadence, spoke on “Cadence System and Verification Vision” and Balajee Sowrirajan, vice president – DS India Lab, Samsung R&D Institute India – Bangalore, spoke on “System Verification Challenges for SoCs Powering the Connected World.”
The conference featured 10 tracks, 92 paper presentations, 5 technology update presentations, a design IP breakout session, technology pods on the latest Cadence® technologies and an exhibition area with booths by Cadence partners and customers.
Companies such as Analog Devices, ARM, Broadcom, eInfochips, Freescale, Hyundai Mobis, IBM, L&T Infosystems, NVIDIA, NXP, OmniPhy, Open-Silicon, PMC-Sierra, Qualcomm, Rambus, Samsung, SanDisk, Sankalp Semiconductor, Sanmina Technology, Seagate, SilabTech, Silicon Image, STMicroelectronics, Tata Motors, Tessolve, Texas Instruments and Xilinx presented papers.
The best paper award winners were:
| TRACK | COMPANY | TITLE |
| RTL-to-Signoff: Digital Implementation | ARM | “3GHz and beyond” – Jumping To The New Performance Spectrum With ARM® Cortex®-A72 |
| RTL-to-Signoff: Front-End Design | Texas Instruments | Seamless Deployment Of MSS With Smart-Scan Solution To Enable Higher Multi-Site Test for Large Scale SoCs |
| RTL-to-Signoff: Signoff | Open-Silicon | Metal Programmable Clock Delay Line |
| Mixed-Signal Design | Texas Instruments | Surviving Eternal Conflict Of Accuracy And Cost – Efficient Analog Mixed Signal Co-simulation With Spectre-XPS-MS |
| Custom IC/Analog Design | STMicroelectronics | Addressing 14FDSOI Custom Routing Complexity Through Existing ST + Cadence Solutions |
| System / Verification: Advanced Verification Methodology | Samsung Research Institute – Bangalore | |
| Incremental And Configurable Verification Strategies For Modern SoCs | ||
| System / Verification: Performance & Debug | SilabTech | Modeling And Verification Using System Verilog In Virtuoso And Incisive Enterprise Simulator (NCSIM) |
| System / Verification: Hardware Assisted HW/SW Development | Freescale Semiconductor | Methods For Enabling BootROM Firmware Code Coverage on Palladium |
| System / Verification: Formal Verification | Qualcomm | SLICE System – SoC Level Inter Connection Extractor |
| PCB Design & IC Packaging | Tata Motors Pune | Advantages Of Cadence Simulation Tools In Automotive ECU Environment |
