Cadence Palladium Z1 addresses the verification and software development challenges from IP through sub-systems and SoCs

Cadence Design Systems, Inc. unveiled the Cadence® Palladium® Z1 enterprise emulation platform, the industry’s first datacenter-class emulation system, delivering up to 5X greater emulation throughput than the previous generation, with an average 2.5X greater workload efficiency than the closest competitor. With enterprise-level reliability and scalability, the Palladium Z1 platform executes up to 2304 parallel jobs and scales up to 9.2 billion gates, addressing the growing market requirement for emulation technology that can be efficiently utilized across global design teams to verify increasingly complex systems-on-chip (SoCs). 

Frank Schirrmeister shares insights on this platform more in the below interview.

1. What is the vision behind introducing New Palladium Z1 enterprise emulation platform?

The vision behind Palladium Z1 was to truly provide an enterprise compute resource that can be used to execute verification and software development workloads of various sizes – from IP to sub-system to full SoCs in their system context. To achieve that, the guiding principle was to achieve a similar level of independence of verification jobs from the available emulation resources as you find in a computer today, for which you simply start a task and don’t have to worry about which memory location it executes in, where it sits on the hard drive etc.

2. What are the challenges that the platform addresses?

Today’s designs contain many IP blocks from standard I/Os like WiFi, USB, PCI Express^® (PCIe^®) to system infrastructure including interconnect, interrupt control, uart, timers and customer specific differentiators like custom accelerators, modems etc. In addition, designs contain many processor cores, both symmetric and asymmetric, homogeneous and heterogeneous. And of course all the software associated with chips needs to be considered, either as part of the core functionality with communication stacks, DSP software or GPU microcode as well as user application software infrastructure as it is found in Android, Linux etc. The Palladium Z1 addresses the verification and software development challenges for these designs from IP through sub-systems and SoCs in their system context.

3. What are the special features of this platform?

The main focus it to increase emulation throughput – being able to execute a queue of verification jobs with different sizes and lengths as fast as possible. The development focus was on productivity, predictability and versatility if use models, allowing emulation to be used for different use models including in-circuit emulation, acceleration, low power verification, software development and virtualization.

• The actual execution of tasks is completely virtualized. Where to execute it within the array of available processing domains in the emulator is decided when the task is scheduled knowing the current utilization the emulator is in. Fine granularity is a must for that – in Palladium Z1 as lows as 4million gates. It allows more tasks to run in parallel. Palladium Z1also allows users to re-shape the tasks to use available processing spots in the system most efficiently.
• The actual connections the emulator connects to can be virtualized in several ways. Both real and virtual connections are necessary to balance remote access and “live” data. Palladium Z1 can do both. Actual connections to USB, Ethernet, PCIe, SATA etc. can be positioned 30 meters away from the rack and can be assigned to the jobs in the system flexibly at runtime without having to manually switch connections. This capability is called “virtual target relocation.” In addition, based on the technology that is used for verification IP and has been made synthesizable in our Accelerated Verification IP (AVIP), the emulator can connect to virtual representations of the environment, like a virtual USB. Both are valid and necessary options to do, for example, driver development and throughput analysis.
• Like in a virtual machine in which you may be running Windows on your Mac or PC at home, users want to access the resources of the executed verification job for offline access to look into snapshots of the hardware/software interaction at any point in time. The Virtual Verification Machine has been introduced with Palladium Z1 and it offers users an offline database that provides an accurate trace of what happened during the verification run. Users can roll forward, backward, set trigger conditions, do hardware/software debug, etc. The system behaves like the actual run on emulation, but is now accessible to large numbers of software and hardware designers and reflects the state accurately, including the memory.
• To make “live” connections accessible remotely, pre-integrated Emulation Development Kits are available for USB and PCI-Express interfaces, providing modeling accuracy, high performance and remote access. Their pre-integration makes them easier to use and adopt “out of the box” as opposed to the user having to assemble individual components to enable software development on external interfaces.

4. What are the benefits for the design engineers?

Some of the key benefits include up to 5X greater emulation throughput – users can work though queues of verification tasks faster and get up to 2.5X greater workload efficiency – more jobs can be executed in parallel. Immediate tangible benefits are up to 2X faster compilation speed and in average up to 50% higher average performance – simply executing the emulation throughput of compile, allocate, run and debug much faster.

The platform scales from IP to full SoC emulation with up 576 million gates per rack. It scales up to 9.2 billion gates with up to 2,304 parallel jobs and its rack-based form factor make it ideal for setup in existing data centers. Datacenter-class reliability availability is achieved for example with redundancy.

Overall, designers get best in class total cost of ownership (TCO) with 8X higher gate density at 92% smaller footprint, 44% better power density and up 22 different use models that the platform can execute.

5. Tell us about the market and application it targets

   Besides its scope from IP though sub-systems to SoCs in their system context, key application domains include mobile, compute server, consumer, wireless networking and GPU/CPU development. Users span from hardware verification engineers, to HW/SW and Firmware engineers to actual software developers bringing up Linux and Android up to the middleware or even benchmarks like AnTuTu executing on it.