MOUNTAIN VIEW, CA, 29th November 2016: BaySand, Codasip, Codeplay and UltraSoC today announced an integrated IoT development platform based on the RISC-V open processor instruction set architecture (ISA). The platform offers an open-standards-based solution that allows designers of systems-on-a-chip (SoCs) for IoT applications to get from concept to silicon with a high level of software integration in record time and substantially de-risks the entire product development process.
This new collaboration will be formally announced at the 5th RISC-V Workshop (Google Quad Campus, Mountain View, CA, 29th November), and combines the following partnership:
– BaySand’s foundational IP and Metal Configurable Standard Cell (MCSC) technology
– Codasip’s extensible Codix Bk RISC-V-compliant processor implementation
– Codeplay’s ComputeSuite software development tools for open standards middleware, and
– UltraSoC’s on-chip debug and analytics architecture
The result is an end-to-end development flow that supports the rapid evolution of IoT systems, enabling timely market entry, in-market feature enhancement and on-going usability and cost optimization, all at the price points demanded in this highly cost-sensitive market.
“RISC-V adoption is accelerating, and the IoT is clearly an arena where an open, independent processor architecture offers very powerful advantages,” said Caroline Gabriel, Research Director of ReThink Research. “But as with any processor architecture, the RISC-V ISA needs a healthy, co-operative ecosystem surrounding it: an ecosystem that puts designers in control and empowers innovation.”
Rick O’Connor, Executive Director of the RISC-V Foundation, commented: “A key part of our mission at the RISC-V Foundation is to bring technology developers together, in a standards-based environment, to build a robust ecosystem around the RISC-V ISA. We’re delighted to see these four leading firms in the RISC-V community coming together to offer such a powerful solution.”
The new platform leverages BaySand’s patented MCSC technology which delivers the power, performance and density advantages of standard cell ASIC technology while reducing NRE and time to market (TTM) and dramatically increasing design flexibility. The company’s UltraShuttle multi project wafers (MPW) and MetalCopy FPGA porting technology help to bring new designs to market quickly, with low risk: they combine with a proven and predictable design flow and a rich IP library to create an ideal solution for IoT class designs.
At the IP level, Codasip’s Codix-Bk IP cores are the industry’s first commercially available RISC-V compliant processors, and are at the heart of the new joint platform offering. They are available in multiple configurations and can be quickly and easily customized to the exact needs of IoT designs via unique application analysis technology and a model-based IP structure.
UltraSoC contributes silicon IP and software tools that enable secure, non-intrusive monitoring and analysis of IoT device behavior. These powerful features ease the task of writing and debugging the software that is intrinsic to the operation of complex ICs; they accelerate first-time bring up of new devices; and the same IP allows robust hardware-based security features that can detect unexpected behavior caused by bugs or by malicious interference (Bare Metal Security™).
At the highest level within the new platform, Codeplay provides developers with an open standards based programming model that extends from device-specific functionalities all the way up to highly abstracted machine learning paradigms such as Google’s TensorFlow. ComputeSuite extends the RISC-V platform with OpenCL™ and SYCL™ allowing applications to target the underlying hardware for highest performance, using standard APIs.
