Agile Analog [8], a leading provider ofsemiconductor analog IP, today announced that they have worked withEnSilica [9], a leading fabless design house focused on custom ASICdesign and supply services, to both fabricate and test their latestanalog IP products, and to validate that their advanced product deliveryprocesses provide maximum benefit to Agile Analog’s end customers. Theproject speeds up the process of proving and qualifying analog IP, andreduces the time-to-market and risk of IC development cycles through arevolutionary top-down delivery of initial IP views.
The integration of analog IP onto a complex silicon chip is atime-consuming process that is exacerbated by the variable quality of
currently available analog IP products. Analog circuits are also verysensitive to their on-chip surroundings so issues during integration andtest can lead to reliability problems during the manufacture and massproduction of such chips. Finally, waiting until the end of analog IPdelivery can both slow down chip planning work, and mean that criticalcustomer feedback is not available until it’s too late.
Agile Analog has developed an in-house system to automatically generateanalog IP (including all associated IP product deliverables) to a highquality, according to customer specifications, and on any siliconprocess technology. This system produces a high-quality final IPdelivery package (FDP), as well as an initial delivery package (IDP).The IDP is available very early and allows customers time to integrateit into their chip development process and provide feedback to beimplemented in the FDP.
EnSilica’s world-class expertise in the design of custom analog,mixed-signal and digital chips was critical to developing a chip architecture together with a re-usable test platform that Agile Analogwill use to test and validate their latest analog IP products. EnSilicahas integrated a number of Agile Analog’s IP products, including theirlatest configurable analog-to-digital converter (ADC) IP [10] andbandgap voltage reference IP [11], onto this System-on-Chip forfabrication in TSMC’s 28nm CMOS technology.
“What Agile Analog has achieved is impressive,” said Ian Lankshear,CEO at EnSilica. “The high quality of their automatically generated IPdeliverables really does save integration time and effort and willbenefit all their customers. Thanks to their comprehensivedocumentation, the integration of their analog IP onto an SoC and thedevelopment of a test setup and procedure was effortless for ourengineers, and most of our work could be done using the IDP, so we wereable to get a significant amount of work done early.”
Tim Ramsdale, CEO at Agile Analog, added: “EnSilica’s extensive chipdesign expertise was amply demonstrated in the re-usable SoC design andtest solution they created. This work will be instrumental to AgileAnalog and will allow us to prove more of our analog IP in siliconquickly and efficiently. The project also served as a pipe-cleaningexercise and EnSilica’s knowledgeable feedback and recommendationshave allowed us to improve our products further.”
Agile Analog’s use of design automation to generate analog IP resultsin products that are guaranteed to be consistent and of high quality.Their innovative approach is transforming the semiconductor market byproducing analog IP that is customized to the application’srequirements and is available on any semiconductor process. The projectwith EnSilica enables Agile Analog to silicon-prove their analog IPproducts [12] more efficiently. This will enable Agile Analog’scustomers to take their chips into production faster and more reliably.
