SAN JOSE, Calif., April 14, 2014 — Xilinx, Inc. and Agilent Technologies Inc. announced Xilinx’s DDR4 memory solution for UltraScale™ devices has completed the Agilent N6462A compliance test running at 2400 Mb/s. As defined by the JEDEC JESD79-4 DDR4 DRAM specification, the Agilent N6462A DDR4 compliance test enables early adopters of DDR4 technology to make critical electrical and timing analysis for characterization and margin testing purposes. The DDR4 memory interface in the Xilinx® UltraScale™ All Programmable FPGAs provides more than 1 Tb/s of memory bandwidth to handle the massive data flow, fast processing, and enormous memory requirements of leading-edge, next-generation system designs in key applications such as video imaging and processing, traffic management, and high-performance computing.
Agilent’s DDR4 BGA interposers allow users to gain access to the DDR4 signals that are critical to DDR4 debug and validation. The interposers work in existing designs and eliminate the need for up-front planning or re-design by providing probe points that enable designers to see the actual clock and data signals using an oscilloscope.
“Together with Agilent, we have given customers the ability to accelerate the development of high-performance memory designs,” said Dave Myron, senior director of FPGA product management at Xilinx. “We are shipping UltraScale FPGAs that offer the industry’s first DDR4 memory solution and successfully meet the rigorous JEDEC standard as demonstrated via Agilent’s test solution.”
“We are pleased to work with Xilinx to demonstrate the robustness of their high-performance memory solution,” said Jay Alexander, vice president and general manager of Agilent’s Oscilloscope and Protocol Division. “Our demonstration shows that users can operate at full speed and characterize high-speed DDR4 signals without impacting the performance of their designs.”
