Design and verification IP address server cache-coherency requirements
SAN JOSE, Calif., May 2, 2017 /PRNewswire/ — Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the industry’s first interface and verification IP solution for Cache Coherent Interconnect for Accelerators (CCIX), an open chip-to-chip interconnect standard that advances the development of a new class of server solutions to address the challenging performance and latency requirements in the growing datacenter market. The Cadence® IP for CCIX, which consists of controller, PHY and verification IP, allows semiconductor manufacturers to develop new products for the enterprise server market more quickly and with greater confidence. The new IP for CCIX further extends the Cadence IP portfolio and Cadence Verification Suite technology, key components of the company’s System Design Enablement strategy.
The proliferation of data-intensive applications along with the constraints of power and cooling are driving datacenters to deploy servers incorporating special-purpose accelerators. These accelerators share memory with processors in a cache-coherent manner and enable a heterogeneous server architecture to seamlessly share data with current speeds up to 25Gbps, reducing latency and increasing performance.
Supported by industry leaders, CCIX is a comprehensive hardware and software solution that builds on the pervasive PCI Express® (PCIe®) technology. The CCIX standard allows processors based on different instruction set architectures to extend the benefits of cache-coherent peer processing to various acceleration devices.
“ARM recognizes that the new CCIX specification supporting cache coherency is extremely important to the enterprise ecosystem,” said Monika Biddulph, general manager, Systems and Software Group, ARM. “Together, the Cadence IP for CCIX and the ARM® CoreLink™ CMN-600 Coherent Mesh Network provide a scalable, heterogeneous compute platform with high performance multichip connectivity that will enable innovative solutions for applications such as machine learning, network processing, storage off-load and analytics.”
The Cadence Interface IP for CCIX is an integrated solution for CCIX based on the PCIe 4.0 specification. The integrated solution for CCIX includes controller, PHY, software drivers, scripts for design and verification, simulation models and user guides. The entire package is pre-verified using Cadence verification IP for CCIX. For more information on the interface IP solution, visit: www.cadence.com/go/ccixdip.
“CCIX enables a new class of interconnect for emerging acceleration applications in the datacenter,” said Gaurav Singh, chairman of the CCIX Consortium. “We are pleased to see Cadence taking a leading role in providing early access to IP products to accelerate CCIX adoption among our member companies.”
The Cadence Verification IP for CCIX supports the Cadence Xcelium™ Parallel Logic Simulator and third-party simulators. It also supports all major languages and methodologies and is used to verify all CCIX specification levels including PHY, transaction and cache coherency. The Cadence Interconnect Validator works with the verification IP for CCIX to ensure correctness and completeness of data as it passes through the fabric. For more information on the verification IP solution, visit: www.cadence.com/go/ccixvip.
“Cadence is a pioneer and industry leader in PCIe, and we’re leveraging our deep expertise in PCIe and cache coherency to develop an innovative solution for CCIX,” said Babu Mandava, senior vice president and general manager of the IP Group at Cadence. “Because our CCIX enterprise development solution is integrated and based on silicon-proven design IP for the PCIe specification, along with mature and comprehensive verification IP, our customers can develop new products for the server market more quickly, with high confidence and shorter time to market. We are encouraged by our early customer engagements.”
