Seamless Integration of Synopsys’ Synplify Pro and Identify RTL Debugger With Microsemi’s Libero SoC Design Suite for FPGA Customers
ALISO VIEJO, Calif. —May 4, 2017—Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, and Synopsys (Nasdaq: SNPS), a global leader in electronic design automation (EDA) software, today announced a multi-year extension of their OEM agreement to bring customized field programmable gate array (FPGA) synthesis tools to Microsemi’s FPGA customers. The companies recently collaborated on Microsemi’s new cost-optimized, low power PolarFire™ mid-range FPGAs, announced in February, and Synopsys also supported Microsemi during the devices’ early access program.
Synopsys’ Synplify Pro® synthesis software and Identify® RTL Debugger are integrated into Microsemi’s Libero SoC Design Suite, a comprehensive suite of design tools used with the company’s FPGA products, including its PolarFire FPGAs. Synopsys’ solutions enable faster design time with area optimization for cost and power, accelerating FPGA development. These capabilities further enable the unique features of Microsemi’s PolarFire FPGAs, such as the industry’s lowest power at mid-range densities with 12.7 Gbps Serializer/Deserializer (SerDes) transceivers, as well as best-in-class security and reliability.
“Extending our longstanding relationship with the Synopsys team enables us to continue leveraging the company’s extensive expertise in synthesis technology while allowing Microsemi’s engineering resources to focus on supporting the advanced features and capabilities unique to our FPGA devices,” said Jim Davis, vice president of software engineering at Microsemi. “Synopsys’ Synplify Pro synthesis software is specifically designed for FPGAs and is well-known as the de facto industry standard for producing high performance, cost-effective designs for these devices.”
Synopsys’ Synplify Pro software is an industry standard tool for producing high performance and high level optimizations with fast runtimes synthesizing the RTL code for large designs on Microsemi’s FPGAs and system-on-chip (SoC) FPGAs. In addition, Synopsys offers Synplify Premier with multi-vendor support and advanced features, including support for Microsemi FPGAs.
Microsemi’s Libero SoC Design Suite offers high productivity with its comprehensive, easy to learn and easy to adopt development tools for designing with the company’s FPGAs including the new cost-optimized PolarFire FPGAs. The suite includes a complete design flow using Synopsys Synplify Pro synthesis software together with Microsemi’s significantly enhanced constraints management, differentiated FPGA debugging suite, SmartDebug and secure production programming solution (SPPS).
“We were pleased to support Microsemi throughout the early access program for PolarFire FPGAs and are proud to be a part of its mid-range FPGA launch,” said Andrew Dauman, vice president of engineering in Verification Group at Synopsys. “The successful release of these unique devices, including early adoption amongst Microsemi’s customer base, is yet another example of our productive technology collaborations and we look forward to continuing this important relationship for all of Microsemi’s FPGA technology.”
Key benefits of Synopsys’ Synplify Pro synthesis software and Identify RTL debugger for Microsemi FPGA customers include:
• Run time acceleration with multi-processing support
• Faster incremental turn-around times with compile point integration
• Best quality of results (QoR) for area and performance
• Broad language support for Verilog, SystemVerilog, VHSIC Hardware Description Language (VHDL) and mixed language design
• Customizable tool command language (TCL) scripting environment for custom flows and reports
• Inference of wide multiplexers, sequential shift, large static random access memory (LSRAM), µSRAM, and math blocks
