SAN JOSE, Calif., July 12, 2016—Cadence Design Systems, Inc. today announced that its implementation and signoff tools have achieved certification on the Intel® third-generation 10nm tri-gate process for customers of Intel Custom Foundry. Intel Custom Foundry utilized a PowerVR GT7200 graphics processing unit (GPU) from Imagination Technologies as part of the certification process.
The tool certification and enablement provide Intel Custom Foundry customers with a complete and integrated system-on-chip (SoC) design flow. Cadence® tools in the flow include:
- Innovus Implementation System: his massively parallel physical implementation system utilizes GigaPlace™placement technology, GigaOpt™ optimization technology and integrated color-/pin-access-/
variability–aware routing and timing closure to deliver high-quality designs with competitive power, performance and area (PPA) targets while accelerating time to market. - Quantus™ QRC Extraction Solution: This solution uses a single Intel Custom Foundry-certified techfile and delivers a faster, scalable solution by supporting both cell-level and transistor-level extractions during design implementation and signoff with best-in-class accuracy versus foundry golden.
- Tempus™ Timing Signoff Solution: This massively parallelized timing signoff solution provides full-chip static timing analysis (STA) with gate-level delay calculation including signal integrity (SI) analysis, advanced on-chip variation analysis, advanced-node functionality required for double-patterning and waveform effects, and optimization for timing and leakage power.
- Voltus™ IC Power Integrity Solution: This cell-level power integrity solution supports comprehensive electromigration and IR-drop (EM/IR) design rules and requirements while providing full-chip system-on-chip (SoC) power signoff accuracy.
- Voltus-Fi Custom Power Integrity Solution: This transistor-level power integrity solution supports comprehensive EM/IR design rules and requirements while providing SPICE-level power signoff accuracy for analog, memory and custom digital IP blocks.
- Spectre® Classic Simulator, Spectre Accelerated Parallel Simulator (APS) and Spectre RF Simulation: These products deliver fast and accurate circuit simulation of complex analog, radio frequency (RF) and mixed-signal circuits with full support for advanced-node device models and parasitics.
For more information on the Cadence tools that are certified, please visit cadence.com/go/icf10nm, and for more information on Intel Custom Foundry, please visit intel.com/foundry.
“Intel Custom Foundry has worked closely with Cadence to deliver an optimized design ecosystem for our customers who are creating innovative, advanced-node designs,” said Dr. Changhong Dai, vice president, Technology and Manufacturing Group, and director, Technology Optimization Solutions at Intel. “The certified Cadence digital implementation, signoff and simulation tools offer our mutual customers a complete and integrated flow and help them achieve superior PPA on Intel’s third-generation tri-gate 10nm process technology.”
“Our PowerVR Series7XT GPUs are designed to provide optimal performance and a seamless user experience for next-generation user interfaces, 3D gaming and GPU compute,” said Graham Deacon, senior director of PowerVR Business Operations, Imagination. “Imagination worked closely with Cadence and Intel Custom Foundry to use our PowerVR GT7200 GPU for this tool certification. This effort is part of ensuring that design flows deliver excellent PPA for our GPUs on Intel’s 10nm process.”
“Our collaboration with Intel Custom Foundry on the certification process provides customers with added confidence that they can overcome design complexity and get to market faster using the Cadence flow on Intel Custom Foundry’s 10nm design platform,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “Intel Custom Foundry’s growing customer base can now create differentiated SoCs on the Intel 10nm process using the full system-level-to-signoff Cadence tool flow.”
