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Tight integration of the full Cadence RTL-to-signoff digital flow enabled Cypress to improve tool throughput and achieve productivity gains
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Spectre XPS next-generation FastSpice simulator evaluation yielded up to 10X turnaround time improvement over its previous flow
SAN JOSE, Calif., May 10, 2016—Cadence Design Systems, Inc. today announced that after an extensive competitive evaluation, Cypress Semiconductor Corp. selected the full Cadence® RTL-to-signoff digital design flow and complete Spectre® circuit simulation platform for all of its 40nm automotive chip designs. The evaluation process showed Cypress the opportunity to dramatically improve its turnaround time and productivity with the Cadence solution when compared with its previous flow.
The Cadence digital flow consists of the Innovus™ Implementation System, the Genus™ Synthesis Solution, the Tempus™ Timing Signoff Solution, Conformal Low Poer and the Quantus™ QRC Extraction Solution. These tools collectively enabled Cypress to achieve improved individual tool throughput and productivity gains. Specifically, the Innovus Implementation System provided Cypress with significant power, performance and area (PPA) benefits.
In particular, low power was a critical requirement for the Cypress 40nm automotive designs. Cypress develops complex designs with multiple power domains that require comprehensive UPF constraints and many timing modes and corners. The Cadence low-power flow offers IEEE 1801 support, and provided Cypress with area and power reductions.
The Spectre circuit simulation platform, including the Spectre Classic Simulator, the Spectre Accelerated Parallel Simulator (APS), the Spectre eXtensive Partitioning Simulator (XPS) and the Spectre RF Option, can provide Cypress with improved accuracy, speed and ease of use. The initial Spectre XPS next-generation FastSpice simulator evaluation yielded up to 10X turnaround time improvement over Cypress’s previous Cadence flow.
“We’re always up against tight deadlines to deliver innovative and reliable designs to our automotive customers,” said Dragomir Nikolic, worldwide CAD director at Cypress. “While looking at the digital offerings from Cadence, specifically the Innovus Implementation System and the Tempus Timing Signoff Solution, we’ve seen an opportunity to improve our quality of results while significantly reducing cycle time. We know these offerings are state of the art in the EDA industry, and we are eager to see the tools in action on our 40nm platform. In addition to low power, reliability and low parts per billion (PPB) defect rates are critical for us. The Innovus Implementation System routing capability enables us to drive those defects even lower for our automotive customers.”
