Cadence has unveiled the next-generation Virtuoso® platform which offers designers an average of 10X performance and capacity improvement across the platform. The platform includes new technologies within the Cadence® Virtuoso Analog Design Environment (ADE) and enhancements to the Cadence Virtuoso Layout Suite to address requirements for automotive safety, medical device and Internet of Things (IoT) applications.
Steve Lewis, Product Marketing Director, CIC and Packaging Group at Cadence shares more insight on this platform in the the interview here:
-
How is Virtuoso different from other solutions in the market?
Cadence Virtuoso is the longest-lasting solution in the industry, now entering its 25th year. Over that period, we have followed our customers from the “sub-micron revolution” to the “nanometer revolution,” working with them and leading in every node along the way. That level of experience combined with tens of thousands real-world examples of helping customers solve their most challenging analog design, implementation and verification issues makes us the clear choice for preparing our customers for the future. That experience and depth of knowledge is unique to Cadence and Virtuoso.
-
Can you please explain how will it address the requirements of automotive, medical and IoT applications?
One of the key tenets of all of the ISO standards is traceability. The standards demand that to be officially certified, a vendor must be able to completely document its process, ensure that all the prescribed tests have been run and specifications have been met, document when tests were run and track which engineers worked on them, and so on. While this level of traceability has been available in the digital domain for some time (i.e. Cadence’s Incisive vManager tool), it has been ad-hoc in the analog domain.
-
How does Virtuoso ADE verifier offer a significant technology advancement?
Previously, information exchanges were typically contained in spreadsheets outside of the Virtuoso framework. As such, they required manual intervention to keep them up to date. The new Virtuoso ADE Verifier brings a new level of integrated traceability to the analog world. Now customers can link together their highest level circuit specifications (i.e. power consumption) with all of the analog tests being developed and analyzed to guarantee the high-level specs are being met. There may situations where ten different blocks all need to be checked for the specification that is being developed by five different engineers. Now, within the Virtuoso ADE Verifier, customers can easily link the specs and all of the analog tests together. Customers can also tell when tests are updated, when there are failures or perhaps when certain tests aren’t running. They can now see these things in an integrated dashboard-style tool, so there is no more guesswork about who is doing what and when will it be done.
-
While moving to advance nodes what kind of challenges and complexities is Virtuoso addressing?
Though it is different for different people, let’s declare here that by advanced node, we are talking about 16nm and below FinFET designs. For advanced node “custom” designs, we advance the tools in both the front-end (design verification) and the back-end (layout). A key technology that Cadence created by working closely with advanced node foundries is something we term, “fast Monte Carlo.” This technology brings together derived mathematics, sensitivity analysis and Monte Carlo statistical analysis to speed up the overall statistical variation process by a factor of 10. This provides tremendous time and resource savings. In layout, we have a dozen different techniques that we bring to solving the complexity of 16nm FinFETs. Coloring, Design Rule Checking (DRC) rule compliance, accelerated pin-to-trunk routing and the use of Module Generator (ModGen) arrays to make interdigitation of transistor fingers simple. A complete set of features can be found on the advanced node landing page on the Cadence web site at http://www.cadence.com/solutions/an/Pages/default.aspx.
-
How does Virtuoso enable Analog device traceability?
By knowing which tests are being run, which engineers are doing the work and which specs are being tested, customers can gain a much better sense of the current status of the analog design. Because Virtuoso ADE Verifier lives within the Virtuoso framework, the data can always be kept up to date without lots of manual intervention and wondering which spreadsheet to use on any given day. The Virtuoso ADE Verifier’s dashboard will tell you where you are in the design cycle and can condition the data in such a way that it can be easily shared with our Incisive vManager tool. Within that tool, customers can see the complete digital status and understand the status of the analog piece, so mixed-signal verification no longer has to be a mystery.
