Highlights:
-
Cadence solution enables UMC customers to mitigate layout-dependent effects in custom/analog designs
-
Customers using the new UMC 28HPCU LDE kit can reduce iterations by up to 2X and speed design convergence by up to 40 percent
SAN JOSE, Calif., April 13, 2016—Cadence Design Systems, Inc. today announced that Cadence®Virtuoso® Layout-Dependent Effects (LDE) Analyzer has been qualified by United Microelectronics Corporation (UMC) to support its 28HPCU process technology. With the rollout of a new UMC 28HPCU LDE kit, UMC customers can use the Cadence solution to mitigate LDE in custom/analog designs, reducing post-layout iterations by up to 2X and accelerating design convergence by up to 40 percent.
S.C. Chien, senior vice president and head of the IP Development and Design Support division at UMC, said, “We are pleased to add the Cadence Virtuoso LDE Analyzer to our 28HPCU design support portfolio. Transistor device characteristics vary with context, placement and density, and the Cadence LDE kit has allowed our customers who createdesigns using the 28HPCU process to seamlessly bridge the gap between their intended and expected results. This savescustomers several steps in the design process to help them accelerate their designs to the production phase.”
The collaboration between UMC and Cadence ensures that all of the following capabilities included with Virtuoso LDE Analyzer are fully enabled for the 28HPCU reference flow:
- LDE-aware simulation: Allows designers to detect the LDE impact early on by creating a simulation netlist with LDE from a layout that does not need to be layout vs. schematic- (LVS-) clean or even fully placed
- LDE electrical constraints: Enable the early detection of mismatches, due to LDE, without having to complete the layout or run simulation
- Layout LDE analysis: Flags large variations in a transistor’s electrical characteristics between schematic assumptions and actual layout with LDE
- Contribution guidelines: Report the contribution of each LDE for every violation identified in the LDE analysis to help designers understand the root cause of the variation
- LDE fixing guidelines: Generate and display actionable layout modifications that, when implemented, reduce the LDE impact on the transistor’s electrical characteristics
