Positioned for next generation high density 400G and terabit interfaces; Enabling the next wave of Ethernet deployment
SAN JOSE, Calif., March 11, 2016 – Xilinx, Inc. today announced it has developed a 16nm FinFET+-based programmable device running 56G transceiver technology using the 4-level Pulse Amplitude Modulation (PAM4) transmission scheme. Recognized by the industry as the most scalable signaling protocol for next-generation line rates, PAM4 solutions will help drive the next wave of Ethernet deployment for optical and copper interconnects by doubling bandwidth on the existing infrastructure. Xilinx is introducing and demonstrating 56G technology innovation now, ahead of general PAM4 availability, to help educate and prepare providers and ecosystem members to make this transition.
“Our customers are already anticipating how to accelerate their next generation applications. We recognize the need to raise awareness of 56G PAM4 technology solutions now, to help prepare them to transition their own designs,” said Ken Chang, vice president of the SerDes technology group at Xilinx. “I am delighted to be able to showcase our technology.”
As trends such as Cloud Computing, Industrial IoT, and Software-Defined Networks continue to accelerate and drive the need for unlimited bandwidth, technology innovations must scale to 50G, 100G, 400G ports, as well as terabit interfaces to maximize port density without increasing cost and power per bit. Next generation, standardized line rates are critical to meeting these ongoing bandwidth requirements. Xilinx is leading in 56G PAM4 standardization efforts within both the Optical Internetworking Forum (OIF) and the Institute of Electrical and Electronics Engineers (IEEE). The company’s 56G PAM4 transceiver technology has been developed to break through the physical limitations of traditional data transmission at such line rates, including insertion loss and crosstalk. It supports copper and optical interconnects for chip-to-chip, module, direct attach cable, or backplane applications. It will enable next generation system designs for beyond terabit line cards, 400G to terabit chassis backplane.
Xilinx teamed with TSMC to ready its PAM4 device for 16nm FinFET+ said TSMC North America vice president, Sajiv Dalal. “This transceiver breakthrough is another milestone in our long and rewarding collaboration with Xilinx. We share a commitment to high-performance computing, and look forward to this demonstration of Xilinx technology leadership later this month.”
Xilinx will be showcasing the 56G PAM4 transceiver technology demonstration at the upcoming OFC show (booth 3457), March 22 – 24, 2016 in Anaheim, California. For additional information on the Xilinx 56G transceiver technology visit http://www.xilinx.com/products/technology/high-speed-serial/56g.html.
