The Indago Debug Platform can improve verification productivity up to 50%.

The complexity of the SoCs in use today have resulted in debugging becoming one of the biggest bottlenecks, both in terms of human effort and verification iterations required, in IC functional verification. A survey of engineers identified debug as taking 50% of verification effort. 

To help tackle this challenge, Cadence is introducing Indago™ Debug Platform with patented root-cause analysis technology that leverages the Big Data concepts to automate the debug process. Adam shares more in the interview…

1. Can you provide an overview of SoC applications and design complexities?

SoC applications are defined by the integration of power-aware digital, analog, and software IP and are typically multiple hundred million gates or larger.

2. Discuss the debug and verification challenges face by semiconductor design engineers? 

In general, semiconductor engineers run 10’s to 100’s of simulation cycles to identify and resolve any given bug.  For example, system integration engineers must identify bugs within the overall SoC including those related to software and hardware interaction.  These verification runs can take hours to days so if the system integration engineer has to iterate, the overall debug process can take days to weeks.

Similarly, verification engineers must identify bugs among design, testbench, and VIP elements of the IP or subsystem.  While the cycle time to gather the right debug data may be shorter, there are typically many more bugs to resolve at this level.  Design engineers typically operate at the IP level and focus on unit-level verification where the number of cycles to resolve bugs is smaller, in part, due to the engineer’s direct knowledge of the design code.

3. How will Indago address these challenges?

The Indago Debug Platform is a paradigm shift in debug.  It reduces debug to two verification cycles by providing automation for root cause analysis and Big Data analysis techniques.  Each type of engineer uses an appropriate Indago App to collect all of the data relevant to their bug in one cycle.  They then use the automation in an appropriate App to rapidly identify the underlying bugs without rerunning the verification engine. This is especially helpful for the design engineer who needs to fast debug during development, the verification engineer who has multiple bugs to resolve, and the integration engineer who needs to reduce long overall debug cycles.  Once the bug is identified and resolved in any level of design or testbench code, the verification is run a second time to verify the fix.

4. What are the effects on verification productivity?

The Indago Debug Platform can improve verification productivity up to 50%.

5. What are the different debug tasks Indago performs?

Initially, the Indago Debug Platform contains 3 Apps. The Indago Debug App is focused on design and testbench debug providing reverse debugging, interactive post-processing, smart log analysis, and more. The Indago Embedded SW App is focused on debugging software running on embedded processors and synchronizes embedded SW and hardware debug data. The Indago Protocol Debug App is focused on debugging issues related to standard protocols and provides the ability to visualize and abstract protocol traffic and events captured by Cadence® Verification IP.

6. Can you share real case examples?

The Indago Debug Platform white paper located here, http://www.cadence.com/products/fv/Indago_Debug_Platform/pages/default.aspx, has an example that shows the complexity, the previous debug process, and the new Indago debug process.