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Home Electronics News

Cadence Announces Next-Generation JasperGold Formal Verification Platform

Electronics Maker by Electronics Maker
June 13, 2015
in Electronics News
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JasperGold formal and formal-assisted technology is integrated into the Cadence System Development Suite delivering up to three-month project verification schedule reduction

HIGHLIGHTS:

  • Unified Cadence Incisive and JasperGold formal verification platform delivers up to 15X performance gain versus previous solutions
  • JasperGold platform, now integrated within the System Development Suite, finds bugs typically three months earlier than existing verification methods
  • JasperGold solution’s powerful formal analysis engines are now integrated with Indago debug platform, automating root-cause analysis and on-the-fly what-if exploration

SAN JOSE, Calif., June 8, 2015— Cadence Design Systems, Inc. announced the next-generationCadence® JasperGold® formal verification platform. This new formal verification solution integrates Cadence Incisive®formal technology and JasperGold technology into a single platform that delivers up to 15X performance improvement versus previous solutions. Moreover, as an integrated part of the Cadence System Development Suite, the JasperGold technology can help to reduce verification schedule by up to three months.

The next-generation JasperGold platform is currently available. For more information visit http://www.cadence.com/news/jaspergold. 

The JasperGold platform significantly improves design quality and efficiency by integrating a comprehensive set of features into one solution, including:

  • Design compilation and formal engine technologies from Incisive® Formal Verifier and Incisive Enterprise Verifier, including the innovative Trident multi-cooperating engines. This enables easy migration for existing Incisive customers and up to 15X performance improvement for both bug-hunting and proof convergence modes.
  • The next-generation JasperGold platform has been fully integrated with the Cadence System Development Suite’s Incisive simulation and Palladium® emulation platforms, and with vManager™ tool to enable comprehensive metric-driven verification. This results in an up to three-month schedule reduction through formal-assisted verification closure.
  • Proven JasperGold Visualize™ and QuietTrace™ technologies, which have been integrated with the Indago™ debug platform to further expand analysis and on-the-fly what-if exploration, helping reduce root-cause debug time up to 5-100X.

“As long-time customers of Incisive formal and simulation solutions, we are impressed with the next-generation JasperGold platform,” stated Mark Dunn, executive vice president at Imagination Technologies. “As well as improved debug and ease-of-use, we’ve achieved a significant increase in performance compared to Incisive Enterprise Verifier, as measured by proof convergence in a given time.”

”Delivering high quality SoC designs efficiently in an era of increasing design complexity is a continuing customer challenge,” stated Oz Levia, vice president of Formal and Automated Verification, System & Verification Group atCadence. “With this next-generation JasperGold platform, we’ve brought together the best of Cadence’s formal verification technologies into a single JasperGold platform and linked that with simulation, emulation, debug and verification management to create a truly compelling and comprehensive solution to this customer challenge.”

Tags: Semiconductor & IC
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