Rahul Deokar, product management director, Cadence Design Systems, Inc.
Cadence recently launched a best-in-class implementation system called Innovus. Innovus is a physical implementation system that offers production proven advantages in power, performance and area (PPA), enabling SoC developers to accelerate their time-to-market schedules.
Rahul Deokar, product management director, Cadence Design Systems, Inc. talks with EM about the value Innovus brings to the physical design process.
What are the key implementation challenges faced by system companies? What was the initiative to introduce Innovus Implementation System?
System companies that are working on complex, advanced-node design face conflicting challenges around meeting requirements for power, performance, and area (PPA) as well as turnaround time (TAT). While both are critical for design success, it can be difficult to achieve optimal PPA with the highest productivity—without making any tradeoffs. At the heart of this challenge is that with traditional place-and-route tools, designers need to break the systems on chip (SoCs) into many small blocks. This approach, in turn, makes it difficult to balance PPA needs with TAT demands. By using Innovus Implementation System, digital designers are equipped to achieve that long-sought-after design nirvana: meeting both PPA and TAT targets without tradeoffs to either.
What are the breakthrough results of this implementation platform which drive success in design?
Innovus provides a typical 10 to 20 percent production-proven advantage in the PPA of the design, along with an up to 10X TAT and capacity gain. The platform is the industry’s first massively parallel implementation solution. It’s built on a next-generation platform with several integrations that result in an easy-to-use core implementation and signoff flow that facilitates better engineering productivity.
Highlight some key features of this platform?
Key Innovus Implementation System features include:
New GigaPlace solver-based placement technology. This engine is slack-driven and topology-/pin access-/color-aware—features that result in optimal pipeline placement, wirelength, utilization and PPA.
Advanced timing- and power-driven optimization engine. This engine is multi-threaded and layer aware, which reduces dynamic and leakage power while enhancing performance.
Unique concurrent clock and datapath optimization engine that includes automated hybrid H-tree generation. With this engine, engineers benefit from better cross-corner variability and can drive maximum performance with reduced power.
Next-generation slack-driven routing with track-aware timing optimization engine. This engine is equipped to address signal integrity early on and to help improve post-route correlation.
Full-flow multi-objective technology, which enables concurrent electrical and physical optimization to avoid local minima, resulting in the most globally optimal PPA
Massively distributed parallel architecture with full-flow multi-threading and multi-scenario acceleration
Tight integration to Tempus™ Timing Signoff solution, Quantus™ QRC Extraction Solution and Voltus™ IC Power Integrity Solution to accurately model the parasitics, timing, signal, and power integrity issues at early stages of the design. With these capabilities, engineers can achieve faster convergence on these electrical metrics, which results in faster design closure.
Which are the targeted users and key applications?
Innovus Implementation System is optimized for industry-leading ARMv8 processors and also for 16/14/10nm FinFET processes targeting mobile, computing and graphics applications. The system is also ideal for more established/mature process nodes targeting Internet of Things (IoT), automotive and industrial applications.
What is Cadence focus in electronics design industry and how do you maintain your leadership in this market?
Today’s SoC design sizes are well over 100M instances. Traditional implementation tools force designers to break the SoC into too many small blocks—1M to 2M instances each. Imagine working on a 100M instance design that is broken up into so many small blocks. There would be a big impact on TAT and overall time to market. Innovus Implementation System brings in a new shift in block design implementation by allowing designers to implement 5-10M+ instance blocks. This unique differentiation will allow Cadence to broaden its leadership position over its competitors.
