Native SystemVerilog-based VIP for PCI Express architecture now supports M-PCIe technology, with built-in coverage, verification plan and protocol-aware debug
Bangalore, October 7, 2014– Synopsys, Inc. a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced the availability of verification IP (VIP) for the M-PCIe™ protocol, including built-in M-PHY® as defined by the MIPI® Alliance specification. Based on its native System Verilog VIP architecture, Synopsys’ VIP for M-PCIe technology enables enhanced performance, ease of use and debug in System Verilog UVM environments. The Synopsys VIP for M-PCIe is integrated with Synopsys’ Verdi® Protocol Analyzer, a protocol-aware environment that speeds debug by providing simplified views of protocol traffic. The addition of M-PCIe technology to Synopsys’ VIP for PCI Express® architecture provides mobile and low power PCI Express design and integration teams with a full-featured, System Verilog UVM solution to accelerate verification and coverage closure.
“As an active PCI-SIG member, Synopsys has been a valued contributor to the advancement of PCIe technology,” said Al Yanes, PCI-SIG chairman and president. “The Synopsys VIP support for the M-PCIe architecture further helps the PCI Express ecosystem attain adoption within an increasing range of platforms.”
“The release of new protocol versions to address new market segments creates a complex and lengthy ramp-up process for design teams as they strive to rapidly verify compliance against the new specification,” said Debashis Chowdhury, vice president of R&D for the Synopsys Verification Group. “We continue to deliver VIP for new versions of protocols to enable our customers to achieve their SoC verification closure goals and accelerate time-to-market. The new Synopsys’ VIP for M-PCIe protocol provides designers with the built-in protocol knowledge, features and methodology support to save time, increase design quality and meet project schedules.”
The VIP for M-PCIe is a part of Synopsys’ comprehensive verification IP portfolio for PCIe, which supports all versions of the PCIe technology and NVMe. Synopsys’ complete M-PCIe IP solution consisting of verification IP, a silicon-proven DesignWare® M-PCIe digital controller and M-PHY enables project teams to accelerate development of M-PCIe-based SoCs and hit critical market windows.
Synopsys will be demonstrating verification IP support for M-PCIe at the MIPI Alliance All Members Meeting in Shanghai October 6-10:http://wwwqa2/IP/Pages/mipi-f2f-shanghai-event.aspx
Availability
Synopsys’ verification IP for M-PCIe is available today for early adopters as a stand-alone title and as part of Synopsys’ Verification IP Library as well as Verification Compiler. The DesignWare M-PCIe digital controller and PHY are available now.www.synopsys.com/vip.
