Both, Parallel and Serial modes of communication have certain advantages and disadvantages over one another. The serial communication is a preferred option due to its ability of long distance communication with error detection capability. The microcontrollers consist of an inbuilt hardware unit to facilitate serial transfer of data.
There are two primary forms of serial transmission: Synchronous and Asynchronous. Depending on the modes that are supported by the hardware, the name of the communication sub-system will usually include Asynchronous communication (UART) or Synchronous communications(USART). The Universal Asynchronous Receiver/Transmitter controller is the key component of the serial communications subsystem of a computer. The UART takes bytes of data and transmits the individual bits in a sequential fashion. At the destination, a second UART re-assembles the bits into complete bytes.Serial transmission is commonly used with modems and for non- networked communication between computers, terminals and other devices. Synchronous serial transmission requires that the sender and receiver share a clock with one another, or that the sender provide a strobe or other timing signal so that the receiver knows when to “read” the next bit of the data. In most forms of serial Synchronous communication, if there is no data available at a given instant to transmit, a fill character must be sent instead so that data is always being transmitted. Synchronous communication is usually more efficient because only data bits are transmitted between sender and receiver, and synchronous communication can be more costly if extra wiring and circuits are required to share a clock signal between the sender and receiver.When a word is given to the UART for Asynchronous transmissions, a bit called the “Start Bit” is added to the beginning of each word that is to be transmitted. The Start Bit is used to alert the receiver that a word of data is about to be sent, and to force the clock in the receiver into synchronization with the clock in the transmitter. After the Start Bit, the individual bits of the word of data are sent, with the Least Significant Bit (LSB) being sent first. Each bit in the transmission is transmitted for exactly the same amount of time as all of the other bits, and the receiver “looks” at the wire at approximately halfway through the period assigned to each bit to determine if the bit is a 1 or a
0.
E U S A R T s t a n d s f o r E n h a n c e d U n i v e r s a l Synchronous Asynchronous Receiver Transmitter. It is a serial I/O communication peripheral and is also known as Serial Communications Interface (SCI). It contains all clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independently of the device program execution. As its name states, apart from the usage of clock for synchronization, this module can also establish asynchronous connection, which makes it irreplaceable in some applications.
For example, in the event that it is difficult or impossible to provide special channels for clock and data transfer (for example, radio remote control or infrared), the EUSART module presents itself as a convenient solution.
EUSART is one of the feature of PIC family controllers that includes
• the ability to wake up from sleep ,when there is activity on the receive pin;
• automatically calculate an incoming baud rate ;
• detect when the receive operation is idle ;
• transmit/receive a 12 bit break character;
• Full-duplex asynchronous transmit and receive;
• Programmable 8- or 9-bit character length;
• Address detection in 9-bit mode;
• Input buffer overrun error detection; and
• Half-duplex communication in synchronous mode (master or slave).
The EUSART transmits and receives data using standard non-return-to-zero (NRZ) format. As seen in figure below, this mode does not use clock signal, while the data format being transferred is very simple:
EUSART Asynchronous Mode
Briefly, each data is transferred in the following way:
• In idle state, data line has high logic level (1);
• Each data transmission starts with START bit which is always a zero (0);
• Each data is 8- or 9-bit wide (LSB bit is first transferred); and
• Each data transmission ends with STOP bit which always has logic level which is always a one (1).
Circuit Diagram
The circuit diagram shows the connection of PIC
18F4550 controller connection to MAX232.Pin 25 and 26 are used for transmitting and receiving.MAX 232 is further interfaced to serial port.
Explanation
In order to enable data transmission via EUSART module, it is necessary to configure it to operate as a transmitter.To do so microcontroller following registers need to be configured.
1.TXSTA (Transmit Status and Control Register)
TXEN = 1 – EUSART transmitter is enabled by setting this bit of the TXSTA register;
SYNC = 0 – EUSART is configured to operate in asynchronous mode by clearing this bit of the TXSTA register; and SPEN = 1 – By setting this bit of the RCSTA register, EUSART is enabled and the TX/CK pin is automatically configured as output. If this bit is simultaneously used for some analog function, it must be disabled by clearing the corresponding bit of the ANSEL register.
The central part of the EUSART transmitter is the shift register TSR which is not directly accessible by the user. In order to start transmission, the module must be enabled by setting the TXEN bit of the TXSTA register. Data to be sent should be written to the TXREG register, which will cause the following sequence of events:
• B y t e w i l l b e i m m e d i a t e l y transferred to the shift register TSR;
• TXREG register remains empty, which is indicated by setting flag bit TXIF of the PIR1 register. If the TXIE bit of the PIE1 register is set, an interrupt will be generated. Besides, the flag is set regardless of whether an interrupt is enabled or not. Also, it cannot be cleared by software, but by writing new data to the TXREG register;
• Control electronics “pushes” data toward the TX pin in rhythm with internal clock: START bit (0) … data … STOP bit (1);
• When the last bit leaves the TSR register, the TRMT bit of the TXSTA regis ter is automatically set;
and
• If the TXREG register has received a new character data in the meantime, the whole procedure is repeated immediately after the STOP bit of the previous character has been transmitted. Sending 9-bit data is enabled by setting the TX9 bit of the TXSTA register. The TX9D bit of the TXSTA register is the ninth and Most Significant data bit. When transferring 9-bit data, the TX9D data bit must be written before writing the 8 least significant bits into the TXREG register. All nine bits of data will be transferred to the TSR shift register immediately after the TXREG write is complete.
2.RCSTA (Receive Status and Control Register)
CREN = 1 – EUSART receiver is enabled by setting this bit of the RCSTA register;
SYNC = 0 – EUSART is configured to operate in asynchronous mode by clearing this bit stored in the TXSTA register; and
SPEN = 1 – By setting this bit of the RCSTA register, EUSART is enabled and the RX/DT pin is automatically configured as input. If this bit is simultaneously used for some analog function, it must be disabled by clearing the corresponding bit of the ANSEL register.
When this first and necessary step is accomplished and START bit is detected, data is transferred to the shift register RSR through the RX pin. When the STOP bit has been received, the following occurs:
• Data is automatically transferred to the RCREG
register (if empty);
• The flag bit RCIF is set and an interrupt, if enabled by the RCIE bit of the PIE1 register, occurs. Similar to transmitter, the flag bit is cleared by software only, i.e. by reading the RCREG register. Bear in mind that this is a two character FIFO memory (first-in, first-out) which allows reception of two characters simultaneously;
• If the RCREG register is occupied (contains two bytes) and the shift register detects new STOP bit, the overflow bit OERR will be set. In this case, a new coming data is lost, and the OEER bit must be cleared by software. It is done by clearing and resetting the CREN bit.
Note: it is not possible to receive new data as far as the OERR bit is set;
• If the STOP bit is zero (0), the FERR bit of the RCSTAregister detecting receive error will be set; and
• To receive 9-bit data it is necessary to set the
RX9 bit of the RCSTA register.
Component Used
PIC18F4550
PIC18F4550 is an 8-bit microcontroller of PIC18 family. PIC18F family is based on 16-bit instruction set architecture. PIC18F4550 consists of 32 KB flash memory, 2 KB SRAM and 256 Bytes EEPROM. This is a 40 pin PIC Microcontroller consisting of 5
I/O ports (PORTA, PORTB, PORTC, PORTD and PORTE). PORTB and PORTD have 8 pins to receive/transmit 8-bit I/O data. The remaining ports have different numbers of pins for I/O data communications.
PIC18F4550 can work on different internal and external clock sources. It can work on a varied range of frequency from 31 KHz to 48 KHz. PIC18F4550 has four in-built timers. There are various inbuilt peripherals like ADC, comparators etc in this controller.
PIC18F4550 is an advanced microcontroller which is equipped with enhanced communication protocols like EUSART, SPI, I2C, USB etc.
Pin Description: MAX 232
The MAX232 IC is used to convert the TTL/CMOS logic levels to RS232 logic levels during serial communication of microcontrollers with PC. The controller operates at TTL logic level (0-5V) whereas the serial communication in PC works on RS232 standards (-25 V to + 25V). This makes it difficult to establish a direct link between them to communicate with each other.
The intermediate link is provided through MAX232. It is a dual driver/receiver that includes a capacitive voltage generator to supply RS232 voltage levels from a single 5V supply. Each receiver converts RS232 inputs to 5V TTL/CMOS levels. These receivers (R1 & R2) can accept ±30V inputs. The drivers (T1 & T2), also called transmitters, convert the TTL/CMOS input level into RS232 level.
MAX 232
The MAX232 IC is used to convert the TTL/CMOS logic levels to RS232 logic levels during serial communication of microcontrollers with PC. The controller operates at TTL logic level (0-5V) whereas the serial communication in PC works on RS232 standards (-25 V to + 25V). This makes it difficult to establish a direct link between them to communicate with each other.
The intermediate link is provided through MAX232. It is a dual driver/receiver that includes a capacitive voltage generator to supply RS232 voltage levels from a single 5V supply. Each receiver converts RS232 inputs to 5V TTL/CMOS levels. These receivers (R1 & R2) can accept ±30V inputs. The drivers (T1 & T2), also called transmitters, convert the TTL/CMOS input level into RS232 level.
The transmitters take input from controller’s serial transmission pin and send the output to RS232’s receiver. The receivers, on the other hand, take input from transmission pin of RS232 serial port and give serial output to microcontroller’s receiver pin. MAX232 needs four external capacitors whose value ranges from 1µF to 22µF.
Programming steps: 1. Configuration of EUSART-
• Set the baud rate by putting appropriate value in the SPBRG register.
• SPEN bit of the RCSTA register is set to high to activate serial port (Tx and Rx pins) of the controller.
• TXEN and CREN bits (in TXSTA and RCSTA registers) are set to high to activate serial transmission and serial reception respectively.
2. For Transmission-
• Store the data into TXREG register.
• Wait until transmission flag (TXIF) is equal to zero (PIR1 register).
3. For Reception-
• Wait until reception flag (RCIF) is equal to zero
(PIR1 register).
• Store the value of RCREG register in some variable. This value is the received data.
